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When debug access is locked, the debug interface remains accessible, but the connection to the Cortex-
M3 core is blocked. This mechanism is controlled by the Authentication Access Port (AAP) as illustrated
by Figure 6.1 (p. 24) .
Figure 6.1. AAP - Authentication Access Port
DEVICEERASE
ERASEBUSY
Cor t e x- M 3
SerialWire
Authentication
debug
interface
SW-DP
Access Port
(AAP)
AHB-AP
The device is unlocked by writing to the AAP_CMDKEY register and then setting the DEVICEERASE
bit of the AAP_CMD register via the debug interface. This erase operation erases the main block, all
lock bits are reset and debug access through the AHB-AP is enabled. The operation takes 40 ms to
complete. Note that the SRAM contents will also be deleted during a device erase.
The debugger may read the status from the AAP_STATUS register. When the ERASEBUSY bit is set
low after DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ
bit in the AAP_CMD register. After reset, the debugger may resume a normal debug session through
the AHB-AP.
Note
If the debug pins are reconfigured for other I/O purposes than debug, a device erase may
no longer be executed. The pins are configured for debug in their reset state.
2011-04-12 - d0001_Rev1.10
24
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